Intel reveals new XBM memory architecture patent to reduce AI memory costs by bypassing HBM silicon interposer.
英特尔专利曝光新型XBM内存架构，拟绕开HBM硅中介层降低AI内存成本
On July 8, Intel revealed a recently filed patent application for a new high-bandwidth memory architecture called Cross-Batch Memory (XBM). This innovative design aims to reduce advanced packaging costs and alleviate the "memory wall" bottleneck faced by AI chips. By eliminating the silicon interposer required for High Bandwidth Memory (HBM) and utilizing UCIe interconnect technology along with an integrated redundancy repair mechanism, XBM enhances efficiency. The patent outlines a back-end transistor (BEOL) DRAM stacking design that maintains packaging dimensions similar to HBM4 while improving scalability and supporting defect repair to boost yield.
Robotics needs a service framework.
RSF defines a common language for robot service capability, lifecycle operations, certification pathways, and service-provider networks.
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